Flexible channel decoding is getting significance with the increase in number of wireless standards and modes within a standard.\r\nA flexible channel decoder is a solution providing interstandard and intrastandard support without change in hardware. However,\r\nthe design of efficient implementation of flexible low-density parity-check (LDPC) code decoders satisfying area, speed, and power\r\nconstraints is a challenging task and still requires considerable research effort. This paper provides an overview of state-of-the-art\r\nin the design of flexible LDPC decoders. The published solutions are evaluated at two levels of architectural design: the processing\r\nelement (PE) and the interconnection structure. A qualitative and quantitative analysis of different design choices is carried out,\r\nand comparison is provided in terms of achieved flexibility, throughput, decoding efficiency, and area (power) consumption.
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